With improvements in performance of information processing apparatuses, such as a communication backbone apparatus or a server, it may be desirable to increase a data rate for transmitting and receiving signals inside and outside the apparatus. Examples of a receiver circuit of a transmission and reception apparatus include a tracking-type receiver circuit in which a phase of a sample clock follows input data and a blind-type receiver circuit in which a phase of a clock does not follow input data.
FIGS. 1A and 1B illustrate a configuration and an operation of a synchronization-type clock data recovery unit of a tracking-type receiver circuit. As illustrated in FIG. 1A, the synchronization-type clock data recovery unit includes a comparator 11, a clock recovery unit (CRU) 12, and a phase interpolator (PI) 13. The comparator 11 determines that an input data signal Vin indicates “0” or “1”, and generates output data Dout. The CRU 12 detects a phase difference between a changing edge of the output data Dout and a changing edge of a clock CLK, and generates a phase interpolation code. For example, one of the changing edges may be a falling edge. The PI 13 shifts the phase of the clock CLK based on a phase interpolation code and generates a clock suitable for sampling the input data signal Vin.
FIG. 1B illustrates operation of a synchronization-type clock data recovery unit in a case in which sampling is performed twice for one period (unit) in the synchronization-type clock data recovery unit. In FIG. 1B, an example is shown in which the sampling is performed at rising edges of the clock CLK and an inverted clock/CLK. The length of one period of the input data signal Vin is similar to but is not the same as the length of one cycle of the clock CLK. When tracking is performed so that the rising edge of the inverted clock/CLK is synchronized with the changing edge of the input data signal Vin, the rising edge of the clock CLK is positioned near the center of one period of the input data signal Vin. In the comparator 11, as shown in FIG. 1A, stable sampling may be performed when the input data signal Vin is sampled at the rising edge of the clock CLK.
A high-speed interface technique involves appropriate control of a parameter of an equalizer or the like in order to adapt to variable components during operation, such as a temperature or a voltage. Accordingly, when a communication failure occurs, it is very difficult to determine the cause of the communication failure through simulations or input and output of digital data. Thus, to include an eye pattern monitor for monitoring an internal waveform of a receiver circuit or an opening degree of an eye pattern may be advantageous in analyzing a communication failure.
FIG. 2 is a diagram that illustrates an eye pattern monitor in a tracking-type receiver circuit. As illustrated in FIG. 2, in the eye pattern monitor, which determines whether it is possible to receive data correctly at each lattice point and indicates a bit error rate, an eye pattern of an input data signal is divided like a lattice in resolution in a time direction and a voltage direction. In FIG. 2, a portion of the figure denoted by E indicates a range in which the input data signal is stable.
Accordingly, in order to obtain an eye pattern, it may be desired to perform a sweep in each of the time direction and the voltage direction. In this case, it may be desired to also continue phase tracking while obtaining the eye pattern because, if the tracking is stopped, the lattice point in the eye pattern being currently measured may be lost. In FIG. 2, P denotes a phase of a changing edge of data, P0 denotes a desirable sampling timing, P1 denotes a phase that undergoes the sweep in order to obtain the eye pattern, L denotes a determination level of the output data Dout, and L1 denotes a level at which the sweep is performed in order to obtain the eye pattern.
When the tracking-type receiver circuit includes PIs, a PI to be used for the determination of a received signal and a PI for an edge to be used for the phase tracking are different circuits and thus, each of the PIs may employ an independent interpolation value. As a result, the timing at which the determination as to whether the data is “0” or “1” is actually performed may be shifted while continuing the phase tracking. Various schemes are proposed for the eye pattern monitor of the tracking-type receiver circuit in which PIs are used to cause a phase of a sample clock to follow input data.
In contrast, in the blind-type receiver circuit, since sampling is performed without causing synchronization with a phase of input data, a data interpolation process for generating data of a data center phase is performed by interpolating sampled data based on detected phase information. Since, in a data interpolation-type reception scheme, a sample phase of data is unable to be moved from a position to which an edge is shifted by 90 degrees, it can be difficult to obtain an eye pattern monitor.
Japanese Laid-open Patent Publication No. 2012-124593, Japanese Laid-open Patent Publication No. 2007-274139, Japanese Laid-open Patent Publication No. 2007-060655, and Japanese Laid-open Patent Publication No. 2011-014973 are examples of related art.